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7 CS 9 . |
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LOGIC SYNTHESIS LAB |
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1. Write a program which reads simple digital circuit (of size up to 10 gates) in blif / Boolean equation and display |
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schematic in graphics format. |
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2. Write a program to convert Blif format into Boolean equation. |
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3. Write a program that estimate area of circuit (specified as Blif or Boolean equation) using library binding technique of |
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simple circuit (up to 10 gates). |
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4. Write a program to implement state machine up to 5 states. |
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5. Write a program to count 4-input lookup table in a simple circuit (up to 10 gates specified as Blif or Boolean equation). |
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6. Write a program to obtain sequencing graph for a given set of arithmetic expression (up to 10 nodes) |
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7. Write VHDL Codes for all gates with all Modeling. |
8. Write VHDL Codes & Test bench for half adder and full adder