Name of Subject  : CAD FOR VLSI DESIGN (8 CS 2)

Unit

Contents

Modern digital systems, complexity and diversity of digital systems, productivity gap and need for CAD tools.

I

Introduction to steps and CAD flow for designing with ASIC and FPGA.

Introduction to VHDL, background, VHDL requirement, Elements of VHDL, top down design, convention and

II

syntax, basic concepts in VHDL i.e. characterizing H/W languages, objects, classes, and signal assignments.

Structural specification of H/W- Parts library, Wiring, modeling, binding alternatives, top down wiring. Design

III

organization and parameterization. Type declaration, VHDL operators.

VHDL subprogram parameters, overloading, predefined attributes, user defined attributes, packaging basic utilities.

IV

VHDL as a modeling language- bi-directional component modeling, multi mode component modeling,

Examples of VHDL synthesis subsets- combinational logic synthesis, sequential circuit synthesis, state machine

V

synthesis. VHDL language grammar. Introduction to synthetic circuits and circuit repositories.