8CS 6 VLSI DESIGN LAB

Simple Design exercises:

01   Half adder, Full adder, Subtractor Flip Flops, 4bit comparator.

02   Parity generator

03   Bit up/down counter with load able count

04   Decoder and encoder

05   8 bit shift register

06   8:1 multiplexer

07   Test bench for a full adder

08   Barrel shifter

09   N by m binary multiplier

10   RISC CPU (3bit opcode, 5bit address)

TOOLS :